Traditionally, memories such as dynamic random access memories (DRAMs) have been designed for low-cost and fast access time. However, gains in cost and access speed have been made via tradeoff decisions resulting in increased power-consumption. A DRAM is made of thousands of transistors organized to form bit cells that store bit-level information. When accessed together, combinations of bit cells can store meaningful and/or useful information. DRAM architectures include signal busses used to activate different combinations of bit cells for writing and/or reading information at addressable storage locations.
Some traditional DRAM architectures are structured such that a DRAM can be operated to quickly retrieve data stored at sequential address locations in response to a single data request and address provided by a processor or memory controller. For example, processors are typically configured to retrieve one or more entire cache lines from DRAM based on a single read request. In a traditional DRAM module, a single conventional read operation requires pre-charging an entire row of bitlines in each DRAM chip of the DRAM module. Each pre-charged row typically corresponds to multiple cache lines.